Event Details

Dielectric-Semiconductor Interface with High-k Gate Dielectrics

  • 2017-08-16
  • Durga Misra, Electrical and Computer Engineering Department, New Jersey Institute of Technology, Newark, NJ 07102, USA.

Low power requirements by the International Technology Road map for Semiconductors (ITRS) dictate integration of high-k metal gates and novel devices such as FinFETs in CMOS technologies. To attend the current trend in device scaling for sub-14 nm CMOS technology (More Moore) EOT scaling of gate dielectric beyond 0.7 nm will be required. Various atomic layer deposition (ALD) methods of HfO2-based high-k gate dielectrics are currently underway to enhance the dielectric constant and reliability in order to meet the above requirements.For example, cyclic deposition of ALD Hf1-xZrxO2 samples where the dielectrics were exposed to intermediate slot plane antenna (SPA) Ar plasma (DSDS).In addition, variation of Al percentage and distribution in HfO2is carried out when HfAlOx and HfO2 are deposited by ALD in a layered structure. To further enhance the device performance, high mobility channel materials with high-k dielectrics are currently being integrated. Substrates like Ge and III-V materials are being considered for their high hole and electron mobility respectively. Electrical performance in these devices depends on the high-k deposition process, precise selection of deposition parameters, predeposition surface treatments and subsequent annealing temperatures. These variations in process conditions significantly impact the nature of the dielectric-semiconductor interface that controls the channel mobility. This talk will outline some of the recent developments of EOT scaling of high-k gate dielectrics on silicon and germanium and how it impacts the interface; and the challenges of obtaining an acceptable interface for high-k on high mobility substrates.